(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly to a method for integrating self-aligned silicide (SALICIDE) field effect transistors (FETs) for logic circuits with dynamic random access memory (DRAM) having self-aligned contacts and capacitors over bit lines (COBs). The method is particularly useful for integrating (embedding) high-density memory with high-performance logic on the same chip.
(2) Description of the Prior Art
Merged logic and memory circuits are finding extensive use in the electronics industry. These circuits, such as microprocessors, are used in the computer industry for general purpose computing. Merged integrated circuits are also used for application-specific circuits (ASC) in other industries, such as automobiles, toys, communications, the like.
To optimize these merged circuits, it is desirable in the electronics industry to form the FETs for the logic and DRAM circuits having different FET process parameters. For example, it is desirable to use a thin gate oxide for the logic FETs and the peripheral circuits for the DRAMs to increase performance (circuit speed), while it is desirable to use a thicker gate oxide, narrower sidewall spacers, and self-aligned contacts (SACs) for the FET access transistors of the DRAM memory cells because of the higher gate voltage (V.sub.g), and also to achieve high density of memory cells and higher yield. It is desirable to integrate the logic and memory circuits on the same chip by using a process that minimizes manufacturing costs.
One method of forming FETs for logic and memory having two different gate oxide thicknesses is described in U.S. Pat. No. 5,668,035 to Fang et al. However, the polycide gate electrodes are of the same thickness and are etched at the same time on both the logic and memory. The application does not address the ability to make sidewall spacers on separate gate electrodes having different widths on the logic and memory. Further, Fang's method does not include making salicide FETs for logic. Huang in U.S. Pat. No. 5,863,820 teaches a method for integrating DRAMs with self-aligned contacts and salicide FETs for logic on the same chip. However, Huang does not teach a method for making memory and logic FETs having different gate-oxide thicknesses and different sidewall-spacer widths. Yoo in U.S. Pat. No. 5,573,980 describes a method for making silicide contacts self-aligned to FET gate electrodes for static RAM cells but does not address merged memory and logic circuits on the same chip. In U.S. Pat. No. 5,472,892 to Gwen et al., a method is disclosed for using a silicide process in making a floating gate memory device and peripheral transistors on the same chip. Lin in U.S. Pat. No. 5,668,065 describes a method for making simultaneously silicide-based self-aligned contacts and logical interconnections, but does not teach integrating memory and logic circuits on the same chip.
Therefore there is still a need in the semiconductor industry to provide a very manufacturable cost-effective process for making merged integrated circuits having salicide FETs for logic circuits and embedded DRAMs with self-aligned node contacts (SACs).